This invention pertains to minimization of low frequency jitter during desynchronization (demapping) of virtual tributary/tributary unit (VT/TU) synchronized data signals into plesiosynchronous data signals.
The SONET/SDH synchronous optical network connection standard uses so-called xe2x80x9cpointersxe2x80x9d to enable movement of synchronous payload envelopes (SPE) across plesiosynchronous (PD)H) boundaries (i.e. between network elements having separate, nearly synchronized clocks) without incurring the delays and data loss associated with the use of large slip buffers for synchronization. Frequency differences between network elements are handled by moving (xe2x80x9cjustifyingxe2x80x9d) the pointers to relocate the SPE within the SONET frame. Unlike slips, pointer justifications do not cause loss of data, but they do cause sudden phase changes. When the payload is demultiplexed from the SONET transport signal, these pointer justification events result in jitter. Low frequency jitter accumulation due to very low frequency pointer justification events can be problematic and difficult to efficiently remove.
One prior art technique for attenuating pointer justification induced low frequency jitter utilizes a phase lock loop (PLY) incorporating a voltage controlled oscillator (VCO) having a frequency characteristic governed by the level of the first-in first-out (FIFO) buffer (sometimes called an xe2x80x9celastic storexe2x80x9d) through which the data stream is processed. However, VCO-based PLL techniques involve comparatively expensive analog circuitry which is difficult to fine tune and which often requires labour intensive xe2x80x9ctweakingxe2x80x9d during manufacture.
Another prior art xe2x80x9cfixed bit leakingxe2x80x9d technique applies a fixed spreading rate to the data stream, with the fixed rate being governed by the maximum jitter frequency offset to be attenuated. However, usage of a fixed rate prevents appropriate jitter attenuation if the jitter frequency offset is close to the nominal clock rate. Disadvantages of the fixed bit leaking technique are addressed by an xe2x80x9cadaptive bit leakingxe2x80x9d prior art technique in which statistical indicia of pointer justification events are accumulated over time, and the speed of the leak rate is varied in an effort to match variations in the statistical indicia. Such adaptation algorithms can successfully attenuate pointer justification induced low frequency jitter, but require complex monitoring of the FIFO buffer depth, and access to the FIFO buffer pointers.
In Cancellation of Pointer Adjustment Jitter in SDH Networks, IEEE Transactions on Communications, Vol. 42, No. 12, December 1994, pp. 3200-3207, Sari et al disclose a closed-loop threshold modulation adaptive phase spreading technique. Although somewhat simpler than the aforementioned adaptive bit leaking and threshold modulation techniques, the closed-loop characteristic of the Sari et al method is inherently complex. U.S. Pat. No. 5,497,405 Elliott et al issued Mar. 5, 1996 discloses an xe2x80x9cOpen Loop Desynchronizerxe2x80x9d which decodes deviations from a nominal bit stuff bit rate to generate a frequency deviation control signal. This signal is used to control a digital filter and a numerically controlled oscillator (NCO). However, the particular method used to derive the frequency deviation control signal is unclear; and, a relatively expensive, accurate digital-to-analog converter having a very high sampling frequency is required.
The present invention facilitates all-digital adaptive attenuation of pointer justification induced low frequency jitter, independently of FIFO buffer depth. Signals transmitted over a SONET/SDH link can be desynchronized (demapped) by a demapper incorporating the invention. The demapper converts the SONET/SDH signal to a plesiosynchronous signal for transmission over a plesiosynchronous link in such a manner that the demapping operation is lossless over time (i.e. the number of bits in equals the number of bits out over time), thus allowing utilization of a FIFO buffer without the need to monitor the buffer""s depth by observing its pointers.
The invention facilitates attenuation of pointer justification event induced low frequency jitter during desynchronization of a synchronous input data stream into a plesiosynchronous output data stream. The output data stream has a clock rate. T and is made up of tb byte multi-frames containing a nominal number tdb of data bits (tdb=772 and tb=104 for T1 data; tdb=1024 and tb=140 for E1 data). An integer number pc of phase adjustment commands are provided (in the preferred embodiment, pc 12 for T1 data and pc=9 for E1 data), A count having a total value pjT, where 1xe2x89xa6pjTxe2x89xa6tb, is maintained of the total number of positive pointer justification events previously encountered in the data stream. A separate count having a total value pcT, where 1xe2x89xa6pcTxe2x89xa6tdb*pc, is maintained of the total number of previously issued phase adjustment commands. If a positive pointer justification event is detected in the data stream, pjT is incremented by one. If a negative pointer justification event is detected in the data stream, pjT is decremented by one. If, at any time, tdb/tb*pjT*pc greater than pcT, then positive phase adjustment commands are issued and pcT is incremented by one for each issued positive phase adjustment command, until tdb/tb*pjT*pc=pcT. If, at any time, tdb/tb*pjT*pc less than pcT, then negative phase adjustment commands are issued and pcT is decremented by one for each issued negative phase adjustment command until tdb/tb*pjT*pc=pcT. The rate of command issuance can be adaptively varied as a function of the magnitude of the difference between pcT and tdb/tb*pjT*pc. The clock rate T is varied by adding the issued positive phase adjustment commands to the clock rate T and subtracting the issued negative phase adjustment commands from the clock rate T as the phase adjustment commands are issued.